Non-planar, three-dimensional device structures are being investigated for use in integrated circuits as a replacement for planar devices, which have limitations on scalability. In particular, fin-type field effect transistors (FinFETs) are low-power, high speed non-planar devices that can be more densely packed on a substrate than traditional planar transistors. In addition, FinFETs also offer superior short channel scalability, reduced threshold voltage swing, higher mobility, and the ability to operate at lower supply voltages than traditional planar transistors.
Integrated circuits that include FinFETs may be fabricated on a bulk silicon substrate or, more commonly, on a silicon-on-insulator (SOI) wafer that includes an active SOI layer of a single crystal semiconductor, such as silicon, a semiconductor substrate, and a buried insulator layer that separates and electrically isolates the semiconductor substrate from the SOI layer. Each FinFET includes a narrow vertical fin body of single crystal semiconductor material with vertically-projecting sidewalls. A gate contact or electrode intersects a channel region of the fin body and is isolated electrically from the fin body by a thin gate dielectric layer. Flanking the central channel region at opposite ends of the fin body are heavily-doped source/drain regions. When a voltage exceeding a characteristic threshold voltage is applied to the gate electrode, a depletion/inversion layer is formed in the channel region that permits carrier flow between the source/drain regions (i.e., the device output current).
A FinFET may be operated in two distinct modes contingent upon the characteristics of the depletion/inversion layer. A FinFET is considered to operate in a partially-depleted mode when the depletion/inversion layer fails to extend completely across the width of the fin body. The undepleted portion of the fin body in the channel region is electrically conductive and slowly charges as the FinFET is switched to various voltages depending upon its most recent history of use. This floating body effect in partially-depleted FinFETs reduces the reproducibility of device operation by changing the body potential during device operation.
A FinFET is considered to operate in a fully-depleted mode when the depletion/inversion layer extends across the full width of the fin body. A fully-depleted FinFET exhibits performance gains in comparison with operation in a partially-depleted mode. Significant reductions in leakage current, because of strong gate control, dissipate less power into the substrate, which reduces the likelihood of device overheating. Furthermore, parasitic capacitances are greatly reduced in fully-depleted FinFETs, which significantly improves the device switching speed.
Because of the advantages of operating a FinFET in a fully-depleted mode, control of the width of the fin body is important for optimizing FinFET performance. Conventional methods of forming the fin body utilize subtractive etching in which a uniformly thick layer of single crystal silicon is patterned by masking and etching with a process like reactive ion etching (RIE). The width of the fin body is related to the line width of a resist mask or a hard mask. The nominal line width is specified either by photolithographic techniques or by sidewall image transfer from an overlying spacer but may be influenced by other factors, as explained below.
Conventional subtractive etching techniques for forming the fin body of a FinFET fail to precisely and accurately define the fin body shape. In particular, subtractive etching unwantedly tapers the width of the fin body by about 10 percent or more. Variations in the fin body width result in unacceptably large variations in the threshold voltage of the FinFET because the threshold voltage varies along the height of the tapered fin body. More specifically, the threshold voltage will be higher near the base of the fin body than near the narrower tip. As a result, the activated FinFET will have a reduced current density near the base and not take advantage of the full device capability.
One persistent source of fin body tapering arises from the minor isotropic component of ideally anisotropic RIE processes. The minor isotropic component will cause the width of the fin body to depend upon the exposure time to the etchant. Consequently, the tip of the fin body, which has a longer exposure time to the etchant, will be slightly thinner than the base of the fin body. Another persistent source of fin body tapering is mask erosion that originates from progressive etching of the mask material during the RIE process. Specifically, the RIE process is non-selective against the mask material. Lateral erosion recedes the edges of the mask material protecting the underlying semiconductor material from the etchant. Because the dimensions change with increasing etching time, the resultant width of the fin body tapers with increasing height.
Conventional FinFET fabrication techniques based upon subtractive etching may introduce large variations in the shape of fin bodies formed across the surface of any single wafer and among multiple wafers in a wafer line. In particular, etchant consumption varies across the wafer surface as a function of feature or pattern density. Specifically, etchant is consumed faster in regions on the wafer surface with high pattern density, which leads to the necessity of overetching in these high pattern density regions to achieve a fully defined fin body. However, the lengthened exposure to the etchant unwantedly results in thinner fin bodies in low pattern density regions than in high pattern density regions. For FinFETs fabricated on a bulk substrate, the height of the fin bodies will vary across the wafer surface because of overetching in high pattern density regions. Changes in the etch loading to compensate for etchant consumption may also cause non-uniformities in the fin body width.
What is needed, therefore, are fin bodies for a FinFET and methods of making the fin bodies with improved precision in shape control that overcome the various disadvantages of conventional semiconductor structures and methods of making such semiconductor structures.